The present invention relates, in general, to electronics and, more particularly, to semiconductor device structures and methods of manufacture.
Through-substrate vias, through-silicon vias, or TSVs have been used in electronics manufacturing to provide a vertically oriented electrical connection scheme extending through a semiconductor wafer or die. TSVs have been used as an alternative interconnect technique to flip-chip interconnects and wire bond interconnects. Also, TSVs have been used to create three-dimensional (3D) integrated circuits, which have smaller foot-prints compared to stacked encapsulated or packaged devices.
In addition, TSVs have been used in interposer structures. Interposer structures are electrical interface structures that route electrical signals between multiple integrated circuit devices, spread the electrical connections to a wider pitch, or reroute the electrical connections to a different connection interface. In the past, copper-filled TSVs have been used in interposer structures and tungsten-filled TSVs have been used as a cost-effective alternative in some thin-substrate applications.
Tungsten-filled TSV's have had a limitation in certain process flows that limit their use to semiconductor substrates less than 100 microns thick. For example, certain etch tools used to form the vias have been limited in forming vias with depths up to only 100 microns, which requires that thinner semiconductor wafers be used. Also, deposition tools used to deposit tungsten have been limited in their ability to fill vias greater than 100 microns in depth. However, certain customer demands require that semiconductor wafers used, for example, in interposer structures, be thicker (e.g., 200 microns to 250 microns thick or thicker) to facilitate handling of the interposers and/or the integrated circuits attached to the interposers. The thicker structures are also required to accommodate larger diameter bumps (e.g., greater than about 150 microns). In addition, some applications have required larger interposer die sizes, for example, greater than 15 millimeters (min) per side, which has not been feasible for a bumped interposer die 100 microns thick or less.
Accordingly, it is desirable to have a method and structure for TSVs that can support, among other things, industry demand for thicker and/or larger die size TSV structures, which are cost-effective, easily integrated into process flows, and supportive of using conductive materials including tungsten. Also, it is desirable for the method and structure to be suitable for use in heat sinking applications.
For simplicity and clarity of the illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current-carrying electrode means an element of a device that carries current through the device, such as a source or a drain of an MOS transistor, an emitter or a collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode means an element of the device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-type regions and certain P-type regions, a person of ordinary skill in the art understands that the conductivity types can be reversed and are also possible in accordance with the present description, taking into account any necessary polarity reversal of voltages, inversion of transistor type and/or current direction, etc. For clarity of the drawings, certain regions of device structures, such as doped regions or dielectric regions, may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that, due to the diffusion and activation of dopants or formation of layers, the edges of such regions generally may not be straight lines and that the corners may not be precise angles. Furthermore, the term major surface when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items. In addition, the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms comprises, comprising, includes, and/or including, when used in this specification, specify the presence of stated features, numbers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof. It will be understood that, although the terms first, second, etc. may be used herein to describe various members, elements, regions, layers and/or sections, these members, elements, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one member, element, region, layer and/or section from another. Thus, for example, a first member, a first element, a first region, a first layer and/or a first section discussed below could be termed a second member, a second element, a second region, a second layer and/or a second section without departing from the teachings of the present disclosure. It will be appreciated by those skilled in the art that words, during, while, and when as used herein related to circuit operation are not exact terms that mean an action takes place instantly upon an initiating action, but that there may be some small but reasonable delay, such as propagation delay, between the reaction that is initiated by the initial action. Additionally, the term while means a certain action occurs at least within some portion of a duration of the initiating action. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment, but in some cases it may. The use of word about, approximately or substantially means a value of an element is expected to be close to a state value or position. However, as is well known in the art there are always minor variances preventing values or positions from being exactly stated. Unless specified otherwise, as used herein the word over or on includes orientations, placements, or relations where the specified elements can be in direct or indirect physical contact. Unless specified otherwise, as used herein the word overlapping includes orientations, placements, or relations where the specified elements can at least partly or wholly coincide or align in the same or different planes. It is further understood that the embodiments illustrated and described hereinafter suitably may have embodiments and/or may be practiced in the absence of any element that is not specifically disclosed herein.